1. Field of the Invention
The present invention relates to a semiconductor device capable of enhancing a coverage of an upper layer thereof, and a method for manufacturing the semiconductor device.
2. Description of the Background Art
FIG. 6 is a sectional view showing a semiconductor device which has been described in Japanese Unexamined Patent Publication No. 8-306664. In FIG. 6, an upper wiring 105 having a wiring width which is almost equal to a contact diameter is provided on a contact 103 formed through an interlayer insulation film 102 provided on a semiconductor substrate 101, and a contact layer pattern 104 (barrier metal) having a greater width than the wiring width is formed between the upper wiring 105 and the contact 103.
The contact layer pattern 104 is bonded to an area corresponding to a bottom face of the upper wiring 105 and that of a sidewall 107 which is bonded to side faces of the upper wiring 105 and a protective pattern 106 patterned on the upper wiring 105.
In the semiconductor device thus formed, the contact layer pattern 104 has a greater width than the wiring width of the upper wiring 105. Therefore, also in the case where a shift of superposition is caused between the upper wiring 105 and the contact 103, they can be connected well.
In the semiconductor device shown in FIG. 6, the protective pattern 106 made of an insulating film is provided on the upper wiring 105, and a horizontal dimension of the sidewall 107 bonded to a surface of the interlayer insulation film 102 is gained by increasing a vertical dimension of the side face to which the sidewall 107 is bonded, thereby increasing a correction range of the shift of superposition.
However, if the total of thicknesses of the upper wiring 105 and the protective pattern 106 is increased, a surface height difference between the interlayer insulation film 102 and the upper wiring 105 and protective pattern 106 becomes greater. Consequently, it is difficult to form an upper layer with a good coverage.
In the semiconductor device shown in FIG. 6, in the case where a plurality of upper wirings 105 are arranged, wirings are connected (short-circuited) through the contact layer pattern 104 if a distance between the wirings 105 is reduced to a minimum dimension. In order to avoid this problem, a method for keeping a sufficient space between the wirings can be given. However, it is hard to obtain high integration of the semiconductor device.